Efficient Radiometric Signature Methods for Cognitive Radio Devices

This thesis presents the first comprehensive study and new methods for radiometric fingerprinting of the Cognitive Radio (CR) devices. The scope of the currently available radio identification techniques is limited to a single radio adjustment. Yet, the variable nature of the CR with multiple levels of parameters and adjustments renders the radiometric fingerprinting much more complex. We introduce a new method for radiometric fingerprinting that detects the unique variations in the hardware of the reconfigurable radio by passively monitoring the radio packets. Several individual identifiers are used for extracting the unique physical characteristics of the radio, including the frequency offset, modulated phase offset, in-phase/quadrature-phase offset from the origin, and magnitude. Our method provides stable and robust identification by developing individual identifiers (classifiers) that may each be weak (i.e., incurring a high prediction error) but their committee can provide a strong classification technique. Weighted voting method is used for combining the classifiers. Our hardware implementation and experimental evaluations over multiple radios demonstrate that our weighted voting approach can identify the radios with an average of 97.7% detection probability and an average of 2.3% probability of false alarm after testing only 5 frames. The probability of detection and probability of false alarms both rapidly improve by increasing the number of test frames

Enhancing an Embedded Processor Core with a Cryptographic Unit for Performance and Security

We present a set of low-cost architectural enhancements to accelerate the execution of certain arithmetic operations common in cryptographic applications on an extensible embedded processor core. The proposed enhancements are generic in the sense that they can be beneficially applied in almost any RISC processor. We implemented the enhancements in form of a cryptographic unit (CU) that offers the programmer an extended instruction set. The CU features a 128-bit wide register file and datapath, which enables it to process 128-bit words and perform 128-bit loads/stores. We analyze the speed-up factors for some arithmetic operations and public-key cryptographic algorithms obtained through these enhancements. In addition, we evaluate the hardware overhead (i.e. silicon area) of integrating the CU into an embedded RISC processor. Our experimental results show that the proposed architectural enhancements allow for a significant performance gain for both RSA and ECC at the expense of an acceptable increase in silicon area. We also demonstrate that the proposed enhancements facilitate the protection of cryptographic algorithms against certain types of side-channel attacks and present an AES implementation hardened against cache-based attacks as a case study

Design and realization of an embedded processor for cryptographic applications

Architectural enhancements are a set of modifications in a general-purpose processor to improve the processing of a given workload such as multimedia applications and cryptographic operations. Employing faster/enhanced arithmetic units for the existing instruction set architecture (ISA), introducing application-specific instructions to the ISA, and adding a new set of registers are common practices employed as architectural enhancements. In this thesis, we introduce and implement a set of relatively low-cost enhancement techniques to accelerate certain arithmetic operations common in cryptographic applications on a configurable and extensible embedded processor core. The proposed enhancements are generic in the sense that they can profitably be applied in many RISC processors. These enhancements are organized into, what we prefer to call as, cryptographic unit (CU) that offers an extended ISA to the programmer. We then present the speedup values obtained for various arithmetic operations and public key cryptography algorithms through these enhancements. Furthermore, hardware overhead of introducing the enhancements to the embedded extensible processor is provided in terms of chip area. Our experimental results show that the proposed architectural enhancements provides significant amount of speedup (up to one order of magnitude) in elliptic curve cryptography and RSA with a conservative increase in hardware. Last but not the least, we demonstrate that the proposed enhancements facilitate protection of cryptographic algorithms against certain side-channel attacks by reporting our case study of AES implementation hardened against cache-based attacks